1. Field of the Invention
The invention relates to a method of fabricating a multi-layered printed wiring board having a blind via-hole.
2. Description of the Prior Art
A method of fabricating a multi-layered printed wiring board having a blind via-hole includes an additive process, a build-up process and so on. For instance, Japanese Unexamined Patent Publication No. 4-118989 has suggested a method of fabricating a multi-layered printed wiring board having a blind via-hole wherein electroless copper-plating process is employed. Hereinbelow is explained the suggested method with reference to Prior Art FIGS. 1A to 1M.
First, as illustrated in FIG. 1A, there is prepared a multi-layered insulating substrate 1 having a thickness in the range of 0.05 mm to 0.2 mm. As illustrated in FIG. 1B, the substrate 1 is formed at a desired location with a through-hole 6. Then, as illustrated in FIG. 1C, the substrate 1 is plated with copper to thereby cover upper and lower surfaces of the substrate 1 and an inner wall surface of the through-hole 6 with a copper film 2.
Then, as illustrated in FIG. 1D, the upper and lower surfaces of the substrate 1 is laminated with alkali-soluble dry films 2a, and thereafter, a mask film 3 for forming an external circuit layer is formed on the dry film 2a above the upper surface of the substrate 1, and a mask film 4 for forming an internal circuit layer is formed on the dry film 2a below the lower surface of the substrate 1. Then, the dry films 2a are exposed to ultra-violet ray 2b through the masks 3 and 4, as illustrated in FIG. 1D. Then, the dry films 2a are etched with copper chloride etching solution in an area other than areas which will make external and internal circuits. Subsequently, the dry films 2a covering areas which will make external and internal circuits are removed with sodium carbonate solution. Those steps are steps in a so-called tenting process. Thus, there is obtained a core on which desired external and internal circuits are formed, as illustrated in FIG. 1E.
Then, one more core illustrated in FIG. 1E is formed. The two cores are thermally compressed at 180.degree. C. for 60 minutes by means of a vacuum pressing machine with a prepreg 5 as a bonding sheet being sandwiched therebetween, as illustrated in FIG. 1F. As a result, there is formed a substrate illustrated in FIG. 1G.
Then, as illustrated in FIG. 1H, dry films 16 are laminated over upper and lower surfaces of the substrate illustrated in FIG. 1G for the purpose of forming a plating-resist over the substrate. The dry films 16 are soluble in organic solvent, and have a thickness in the range of 25 to 50 .mu.m. Then, mask films 10 are formed on the dry films 16. Thereafter, the dry films 16 are exposed to ultra-violet ray 2b through the mask films 10 to thereby cure a portion of the dry films 16 at which a through-hole 13 (see FIG. 1M) having a diameter in the range of 0.2 mm to 2.0 mm is to be formed. Then, an unexposed or uncured portion of the dry films 16 are developed and removed by organic solvent such as 1-1-1 trichloroethane. Thus, there is formed a plating-resist 11 covering an area other than an area at which the through-hole 13 is to be formed in the upper and lower surfaces of the substrate. FIG. 1I illustrates the substrate on which the patterned plating-resist 11 is formed.
Then, as illustrated in FIG. 1J, the substrate is formed at a desired location with a through-hole 7. Then, as illustrated in FIG. 1H, a palladium catalyst film 17 is formed over both the upper and lower surfaces of the substrate and an inner wall surface of the through-hole 7. Thereafter, the palladium catalyst film 17 formed on the upper and lower surfaces of the substrate is removed by polishing. As a result, the palladium catalyst film 17 remains only on the inner wall surface of the through-hole 7, as illustrated in FIG. 1L.
Then, in accordance with conventional electroless additive process, an electroless copper-plating film 18 is formed on the inner wall surface of the through-hole 17 by employing electroless copper-plating solution containing formalin therein, as illustrated in FIG. 1M. The copper-plating film 18 establishes electrical communication between the upper and lower surfaces of the substrate. As is obvious in FIG. 1M, the through-hole 6 becomes blind. Thus, there is completed a multi-layered printed wiring board having a blind via-hole.
In the above-mentioned conventional method of fabricating a multi-layered printed wiring board having a blind via-hole, a through-hole, an external circuit pattern, and upper and lower surfaces of a substrate are not electrically conductive, after the two cores are connected to each other by compression, as illustrated in FIG. 1F. In order to make them electrically conductive, only electroless plating may be used. However, the electroless plating is accompanied with problems of environmental pollution caused by formalin contained in electroless plating solution, and an increase in fabrication cost.
In the above-mentioned conventional method, an unnecessary portion of the palladium catalyst film 17 formed on the upper and lower surfaces of the substrate is removed by polishing, as mentioned earlier. However, it would be quite difficult or almost impossible to completely remove the palladium catalyst film 17 only by polishing.
Furthermore, since the upper and lower surfaces of the substrate is electrically communicated only by electroless copper-plating, as mentioned with reference to FIG. 1M, it takes much time to complete plating. Specifically, it takes about 10 hours for forming the copper plating film 18 by electroless copper-plating. In addition, the plating resist 11 is sometimes peeled off and/or dissolved in plating solution, resulting in a problem that a short-circuit occurrence rate caused by the plating resist 11 being peeled off and/or dissolved is quite high, specifically, in the range of 10% to 15%.